Modern control units of this type frequently operate via adaptive algorithms, whose parameters are individually adapted over time to the machine, for example the engine of a motor vehicle, to be controlled. For this purpose the control unit must be able to store the parameters for these algorithms which are optimized over time. EEPROMs or SRAMs in particular are used as memories for such data. SRAMs (statically buffered RAM) are primarily used due to the long write times required for EEPROMs.
In order to retain their data content, SRAMs require a continuously applied supply voltage. Following an outage of the supply voltage the contents of these memories may become corrupted, and control based on the corrupted parameters is no longer able to provide accurate results. It is therefore desirable to be able to reliably recognize a power failure in order to prevent the use of parameters whose accuracy can no longer be guaranteed.
Various methods have been provided for detecting a power failure. A first approach is the direct, continuous monitoring of the supply voltage by comparing it to a minimum voltage which is possibly dependent on the type of data memory used and if the voltage is less than this minimum voltage it may be assumed that a loss has occurred, or at least it may be assumed with a high degree of probability that the data are corrupt. However, such monitoring is possible only when the circuit itself, which is used for the monitoring, still reliably functions at the minimum voltage. For voltages of 1.5 V and less in modern controllers, this requirement cannot be easily met.
Further approaches for recognizing a power failure are based on indirect detection based on memory contents corrupted as the result of a power failure. Thus, for example, check sums of the memory contents computed at different points in time may be compared to one another in order to draw a conclusion, based on a deviation between the check sums, concerning a power failure between the two points in time. However, the check sum computation is time-intensive, which is particularly burdensome when the computation delays startup of the machine controlled by the control unit.
According to a further approach, predetermined test patterns are stored in a designated area of the memory, from time to time they are compared with the setpoint value, and in the event of a deviation from the setpoint value a power failure is identified. A disadvantage of this approach, however, is that the memory area used for the test patterns is not available for other purposes. In addition, there is the risk that various cells in the memory to be monitored may have different periods of tolerance for power failures. As long as there is a lack of certainty that the memory cells containing the test patterns are the ones most sensitive to a power failure, the integrity of the test pattern cannot be used to support a definitive conclusion that no power failure has occurred.
The trend toward miniaturization of the circuit structures of modern semiconductor memories has resulted in increased sensitivity to ionizing radiation. This radiation may be of cosmic origin in particular, but may also result from radioactive decay in the solder or the housing of the semiconductor circuit. The charge quantities which account for the difference between two different logical levels of a modern highly integrated circuit have become so small that a single quantum of ionizing radiation that is absorbed by a semiconductor structure may be sufficient to invert the logical state of the semiconductor. To enable detection of and response to such spontaneous state transitions, also referred to as “bit flip,” a parity bit may be associated with a data word in such a memory, the parity bit being read together with the data word. A discrepancy between the parity of the read data word and the associated read parity bit indicates a bit flip.
As the resolution of semiconductor structures becomes increasingly finer, the higher is the probability that an observed parity error is radiation-induced, so that, based on the occurrence of such a parity error, it is not possible to definitively conclude that a power failure has occurred.